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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com ? ? ? ? xr16c864 2.97v to 5.5v quad uart with 128-byte fifo april 2004 rev. 2.0.1 general description the xr16c864 1 (864) is an enhanced quad universal asynchronous receiver and transmitter (uart) each with 128 bytes of transmit and receive fifos, transmit and receive fifo counters and trigger levels, automatic hardware and software flow control, automatic rs-485 half-duplex direction control and data rates of up to 2 mbps. each uart has a set of registers that provide the user with operating status and control, receiver error indications, and modem serial interface controls. system interrupts may be tailored to meet design requirements. an internal loopback capability allows onboard diagnostics. the 864 is available in the 100- pin qfp package. the xr16c864 offers faster channel status access by providing separate outputs for txrdy and rxrdy, offer separate infrared tx outputs and a separate clock input for channel c (chcclk). the xr16c864 is compatible with the industry standard st16c554/554d, st16c654/654d and xr16c854/854d. n ote : 1 covered by u.s. patent #5,649,122 and #5,949,787. features added feature in devices with top mark date code of "f2 yyww" and newer: n 5 volt tolerant inputs 2.97 to 5.5 volt operation pin-to-pin compatible with the industry standard st16c554 and st16c654 and tis tl16c554n and tl16c754bfn intel or motorola data bus interface select four independent uart channels n register set compatible to 16c550 n data rates of up to 2 mbps n transmit and receive fifos of 128 bytes n programmable tx and rx fifo trigger levels n transmit and receive fifo level counters n automatic hardware (rts/cts) flow control n selectable auto rts flow control hysteresis n automatic software (xon/xoff) flow control n wireless infrared (irda 1.0) encoder/decoder sleep mode (200 ua typical) crystal oscillator or external clock input applications portable appliances telecommunication network routers ethernet network routers cellular data devices factory automation and process controls f igure 1. xr16c864 b lock d iagram xtal1 xtal2 crystal osc/buffer intel or motorola data bus interface uart channel a 128 byte tx fifo 128 byte rx fifo brg ir endec tx & rx uart regs 2.97v to 5.5v vcc 854 blk txb, rxb, irtxb, dtrb#, dsrb#, rtsb#, ctsb#, cdb#, rib#, op2b#, op1b#/rs-485 uart channel b (same as channel a) a2:a0 d7:d0 cs# a-d 16/68# int a-d iow# ior# reset intsel chcclk txrdy# a-d rxrdy# a-d uart channel c (same as channel a) txa, rxa, irtxa, dtra#, dsra#, rtsa#, ctsa#, cda#, ria#, op2a#, op1a#/rs-485 txc, rxc, irtxc, dtrc#, dsrc#, rtsc#, ctsc#, cdc#, ric#, op2c#, op1c#/rs-485 uart channel d (same as channel a) txd, rxd, irtxd, dtrd#, dsrd#, rtsd#, ctsd#, cdd#, rid#, op2d#, op1d#/rs-485 5v tolerant inputs (except xtal1) tc aen dack a-d txdrq# a-d rxdrq# a-d direct memory access bclk a-d clksel
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 2 f igure 2. xr16c864 p in o ut a ssignment i n 16 and 68 m ode xr16c864 100-pin qfp 16 mode connect 16/68# pin to vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 bclka op2a# op1a#/rs-485 dacka txrdya#/txdrqa# irtxa dsra# ctsa# dtra# vcc rtsa# inta csa# txa iow# txb csb# intb rtsb# gnd dtrb# ctsb# dsrb# irtxb txrdyb# dackb aen op1b#/rs-485 op2b# bclkb rxrdyb#/rxdrqb cdb# rib# rxb clksel 16/68# a2 a1 a0 xtal1 xtal2 chcclk reset rxrdy# txrdy# gnd rxc ric# cdc# rxrdyc#/rxdrqc bclkd op2d# op1#/rs485 dackd fsrs# irtxd dsrd# ctsd# dtrd# gnd rtsd# intd csd# txd ior# txc csc# intc rtsc# vcc dtrc# ctsc# dsrc# irtxc txrdyc#/txdrqc dackc tc op1c#/rs-485 op2c# bclkc rxrdya#/rxdrqa cda# ria# rxa gnd d7 d6 d5 d4 d3 d2 d1 d0 intsel vcc rxd rid# cdd# rxrdyd#/rxdrqd txrdyd#/txdrqd xr16c864 100-pin qfp 68 mode connect 16/68# pin to gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 bclka op2a# op1a#/rs-485 dacka txrdya#/txdrqa# irtxa dsra# ctsa# dtra# vcc rtsa# irq# cs# txa r/w# txb a3 n.c. rtsb# gnd dtrb# ctsb# dsrb# irtxb txrdyb# dackb aen op1b#/rs-485 op2b# bclkb rxrdyb#/rxdrqb cdb# rib# rxb clksel 16/68# a2 a1 a0 xtal1 xtal2 chcclk reset# rxrdy# txrdy# gnd rxc ric# cdc# rxrdyc#/rxdrqc bclkd op2d# op1#/rs485 dackd fsrs# irtxd dsrd# ctsd# dtrd# gnd rtsd# n.c. n.c. txd n.c. txc a4 n.c. rtsc# vcc dtrc# ctsc# dsrc# irtxc txrdyc#/txdrqc dackc tc op1c#/rs-485 op2c# bclkc rxrdya#/rxdrqa cda# ria# rxa gnd d7 d6 d5 d4 d3 d2 d1 d0 gnd vcc rxd rid# cdd# rxrdyd#/rxdrqd txrdyd#/txdrqd
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 3 pin descriptions ordering information p art n umber p ackage o perating t emperature r ange d evice s tatus xr16c864cq 100-lead qfp 0c to +70c active xr16c864iq 100-lead qfp -40c to +85c active pin description n ame 100-qfp p in # t ype d escription data bus interface a2 a1 a0 37 38 39 i address data lines [2:0]. these 3 address lines select one of the internal registers in uart channels a-d during a data bus transaction. d7 d6 d5 d4 d3 d2 d1 d0 95 94 93 92 91 90 89 88 i/o data bus lines [7:0] (bidirectional). ior# (n.c.) 66 i when 16/68# pin is at logic 1, the intel bus interface is selected and this input becomes read strobe (active low). the falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [a2:a0], puts the data byte on the data bus to allow the host processor to read it on the rising edge. when 16/68# pin is at logic 0, the motorola bus interface is selected and this input is not used. iow# (r/w#) 15 i when 16/68# pin is at logic 1, it selects intel bus interface and this input becomes write strobe (active low). the falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. when 16/68# pin is at logic 0, the motorola bus interface is selected and this input becomes read (logic 1) and write (logic 0) signal. csa# (cs#) 13 i when 16/68# pin is at logic 1, this input is chip select a (active low) to enable channel a in the device. when 16/68# pin is at logic 0, this input becomes the chip select (active low) for the motorola bus interface. csb# (a3) 17 i when 16/68# pin is at logic 1, this input is chip select b (active low) to enable channel b in the device. when 16/68# pin is at logic 0, this input becomes address line a3 which is used for chan- nel selection in the motorola bus interface. csc# (a4) 64 i when 16/68# pin is at logic 1, this input is chip select c (active low) to enable channel c in the device. when 16/68# pin is at logic 0, this input becomes address line a4 which is used for chan- nel selection in the motorola bus interface.
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 4 csd# (n.c.) 68 i when 16/68# pin is at logic 1, this input is chip select d (active low) to enable channel d in the device. when 16/68# pin is at logic 0, this input is not used. inta (irq#) 12 o (od) when 16/68# pin is at logic 1 for intel bus interface, this ouput becomes channel a inter- rupt output. the output state is defined by the user and through the software setting of mcr[3]. inta is set to the active mode when mcr[3] is set to a logic 1. inta is set to the three state mode when mcr[3] is set to a logic 0 (default). see mcr[3]. when 16/68# pin is at logic 0 for motorola bus interface, this output becomes device inter- rupt output (active low, open drain). an external pull-up resistor is required for proper operation. intb intc intd (n.c.) 18 63 69 o when 16/68# pin is at logic 1 for intel bus interface, these ouputs become the interrupt outputs for channels b, c, and d. the output state is defined by the user through the soft- ware setting of mcr[3]. the interrupt outputs are set to the active mode when mcr[3] is set to a logic 1 and are set to the three state mode when mcr[3] is set to a logic 0 (default). see mcr[3]. when 16/68# pin is at logic 0 for motorola bus interface, these outputs are unused and will stay at logic zero level. leave these outputs unconnected. intsel 87 i interrupt select (active high, input with internal pull-down). when 16/68# pin is at logic 1 for intel bus interface, this pin can be used in conjunction with mcr bit-3 to enable or disable the int a-d pins or override mcr bit-3 and enable the interrupt outputs. interrupt outputs are enabled continuously by making this pin a logic 1. making this pin a logic 0 allows mcr bit-3 to enable and disable the interrupt out- put pins. in this mode, mcr bit-3 is set to a logic 1 to enable the continuous output. see mcr bit-3 description for full detail. this pin must be at logic 0 in the motorola bus inter- face mode. txrdya# txrdyb# txrdyc# txrdyd# 5 25 56 81 o uart channels a-d transmitter ready (active low). these outputs provide the tx fifo/ thr status for transmit channels a-d. see ta b l e 5 . if direct memory access is enabled, these outputs become transmit direct memory access request outputs. see txdrq pin description for more details. if these outputs are unused, leave them unconnected. rxrdya# rxrdyb# rxrdyc# rxrdyd# 100 31 50 82 o uart channels a-d receiver ready (active low). these outputs provide the rx fifo/ rhr status for receive channels a-d. see ta b l e 5 . if direct memory access is enabled, these outputs become receive direct memory access request outputs. see rxdrq pin description for more details. if these outputs are unused, leave them unconnected. txrdy# 45 o transmitter ready (active low). this output is a logically wire-ored status of txrdy# a-d. see ta b l e 5 . if this output is unused, leave it unconnected. rxrdy# 44 o receiver ready (active low). this output is a logically wire-ored status of rxrdy# a-d. see ta b l e 5 . if this output is unused, leave it unconnected. fsrs# 76 i fifo status register select (active low input with internal pull-up). the content of the fstat register is placed on the data bus when this pin becomes active. however it should be noted, d0-d3 contain the inverted logic states of txrdy# a-d pins, and d4-d7 the logic states (un-inverted) of rxrdy# a-d pins. address line is not required when reading this status register. direct memory access interface pin description n ame 100-qfp p in # t ype d escription
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 5 tc 54 i direct memory access terminal count. a high pulse terminates a direct memory access transaction. if direct memory access is not used, this input should be connected to gnd. aen 27 i address enable for direct memory access. a high at this input indicates a valid direct memory access cycle. see dack pin descriptions below for direct memory access cycle description. if direct memory access is not used, this input should be connected to gnd. dacka dackb dackc dackd 4 26 55 77 i direct memory access acknowledge. direct memory access cycle will start processing when cpu/host sets this input low and aen high. all writes will be to the tx fifo and all reads will be from the rx fifo. a0-a2 and cs# a-d will be ignored. if direct memory access is not used, these inputs should be connected to vcc. txdrqa txdrqb txdrqc txdrqd 5 25 56 81 o transmit direct memory access request. a transmit empty request is indicated by a high level on txdrq. the txdrq line is held high until either tc pulses or the tx fifo is filled above its trigger level. transmit direct memory access request is enabled by set- ting emsr register bit-2 = 1. if direct memory access is not used, leave these outputs unconnected. rxdrqa rxdrqb rxdrqc rxdrqd 100 31 50 82 o receive direct memory access request. a receive ready request is indicated by a high level on rxdrq. the rxdrq line is held high until either tc pulses or the rx fifo is emptied. receive direct memory access request is enabled by setting emsr register bit-3 = 1. if direct memory access is not used, leave these outputs unconnected. modem or serial i/o interface txa txb txc txd 14 16 65 67 o uart channels a-d transmit data and infrared transmit data. standard transmit and receive interface is enabled when mcr[6] = 0. in this mode, the tx signal will be a logic 1 during reset, or idle (no data). infrared irda transmit and receive interface is enabled when mcr[6] = 1. in the infrared mode, the inactive state (no data) for the infrared encoder/decoder interface is a logic 0. irtxa irtxb irtxc irtxd 6 24 57 75 o uart channels a-d infrared transmit data. the inactive state (no data) for the infrared encoder/decoder interface is a logic 0. regardless of the logic state of mcr bit-6, this pin will be operating in the infrared mode. rxa rxb rxc rxd 97 34 47 85 i uart channels a-d receive data or infrared receive data. normal receive data input must idle at logic 1 condition. the infrared receiver pulses typically idles at logic 0 but can be inverted by software control prior going in to the decoder, see fctr[2]. rtsa# rtsb# rtsc# rtsd# 11 19 62 70 o uart channels a-d request-to-send (active low) or general purpose output. this output must be asserted prior to using auto rts flow control, see efr[6], mcr[1], fctr[1:0], emsr[5:4] and ier[6]. also see figure 10 . if these outputs are not used, leave them unconnected. ctsa# ctsb# ctsc# ctsd# 8 22 59 73 i uart channels a-d clear-to-send (active low) or general purpose input. it can be used for auto cts flow control, see efr[7], and ier[7]. also see figure 10 . these inputs should be connected to vcc when not used. pin description n ame 100-qfp p in # t ype d escription
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 6 dtra# dtrb# dtrc# dtrd# 9 21 60 72 o uart channels a-d data-terminal-ready (active low) or general purpose output. if these outputs are not used, leave them unconnected. dsra# dsrb# dsrc# dsrd# 7 23 58 74 i uart channels a-d data-set-ready (active low) or general purpose input. this input should be connected to vcc when not used. cda# cdb# cdc# cdd# 99 32 49 83 i uart channels a-d carrier-detect (active low) or general purpose input. this input should be connected to vcc when not used. ria# rib# ric# rid# 98 33 48 84 i uart channels a-d ring-indicator (active low) or general purpose input. this input should be connected to vcc when not used. op1a# op1b# op1c# op1d# 3 28 53 78 o general purpose output or rs-485 direction control signal. rs-485 direction control can be selected via fctr bit-3. see auto rs485 half-duplex control on page 18. if these outputs are unused, leave them unconnected. op2a# op2b# op2c# op2d# 2 29 52 79 o general purpose output. if these outputs are unused, leave them unconnected. ancillary signals xtal1 40 i crystal or external clock input. this input is not 5v tolerant. xtal2 41 o crystal or buffered clock output. bclka bclkb bclkc bclkd 1 30 51 80 o baud rate generator output. the baud rate generator clock output is internally con- nected to the rclk input. this pin provides the 16x clock of the selected data rate from the baud rate generator. 16/68# 36 intel or motorola bus select (input with internal pull-up). when 16/68# pin is at logic 1, 16 or intel mode, the device will operate in the intel bus type of interface. when 16/68# pin is at logic 0, 68 or motorola mode, the device will operate in the motor- ola bus type of interface. clksel 35 i baud-rate-generator input clock prescaler select for channels a-d. this input is only sampled during power up or a reset. connect to vcc for divide by 1 and gnd for divide by 4. mcr[7] can override the state of this pin following a reset or initialization. see mcr bit-7 and figure 5 in the baud rate generator section. pin description n ame 100-qfp p in # t ype d escription
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 7 pin type: i=input, o=output, i/o= input/output, od=output open drain. factory test mode if the ior#, iow# and cs# pins are all asserted (at a logic 0), the 864 will enter a factory test mode. chcclk 42 i this input provides the clock for uart channel c. an external 16x baud clock or the crystal oscillators output, xtal2, must be connected to this pin for normal operation. this input may also be used with midi (musical instrument digital interface) applications when an external midi clock is provided. reset (reset#) 43 i when 16/68# pin is at logic 1 for intel bus interface, this input becomes the reset pin (active high). in this case, a 40 ns minimum logic 1 pulse on this pin will reset the internal registers and all outputs. the uart transmitter output will be held at logic 1, the receiver input will be ignored and outputs are reset during reset period ( tab l e 1 8 ). when 16/68# pin is at a logic 0 for motorola bus interface, this input becomes reset# pin (active low). this pin functions similarly, but instead of a logic 1 pulse, a 40 ns minimum logic 0 pulse will reset the internal registers and outputs. vcc 10, 61, 86 pwr 2.97v to 5.5v power supply. all input pins, except xtal1, are 5v tolerant. gnd 20, 46, 71, 96 pwr power supply common, ground. pin description n ame 100-qfp p in # t ype d escription
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 8 1.0 product description the xr16c864 (864) integrates the functions of 4 enhanced 16c550 universal asynchronous receiver and transmitter (uart). each uart is independently controlled having its own set of device configuration registers. the configuration registers set is 16550 uart compatible for control, status and data transfer. additionally, each uart channel has 128-bytes of transmit and receive fifos, automatic rts/cts hardware flow control with hysteresis control, automatic xon/xoff and special character software flow control, programmable transmit and receive fifo trigger levels, fifo level counters, infrared encoder and decoder (irda ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4, and data rate up to 2 mbps. the xr16c864 can operate at 3.3 or 5 volts. the 864 is fabricated with an advanced cmos process. enhanced fifo the 864 quart provides a solution that supports 128 bytes of transmit and receive fifo memory, instead of 64 bytes provided in the st16c654 and 16 bytes in the st16c554, or one byte in the st16c454. the 864 is designed to work with high performance data communication systems, that require fast data processing time. increased performance is realized in the 864 by the larger transmit and receive fifos, fifo trigger level control, fifo level counters and automatic flow control mechanism. this allows the external processor to handle more networking tasks within a given time. for example, the st16c554 with a 16 byte fifo, unloads 16 bytes of receive data in 1.53 ms (this example uses a character length of 11 bits, including start/stop bits at 115.2kbps). this means the external cpu will have to service the receive fifo at 1.53 ms intervals. however with the 128 byte fifo in the 864, the data buffer will not require unloading/loading for 12.2 ms. this increases the service interval giving the external cpu additional time for other applications and reducing the overall uart interrupt servicing time. in addition, the programmable fifo level trigger interrupt and automatic hardware/software flow control is uniquely provided for maximum data throughput performance especially when operating in a multi-channel system. the combination of the above greatly reduces the cpus bandwidth requirement, increases performance, and reduces power consumption. data rate the 864 is capable of operation up to 2 mbps at 5v with 16x internal sampling clock rate. the device can operate with a crystal oscillator of up to 24 mhz crystal on pins xtal1 and xtal2, or external clock source of 32 mhz on xtal1 pin. with a typical crystal of 14.7456 mhz and through a software option, the user can set the prescaler bit for data rates of up to 921.6 kbps. enhanced features the rich feature set of the 864 is available through the internal registers. automatic hardware/software flow control, selectable transmit and receive fifo trigger levels, selectable baud rates, infrared encoder/decoder interface, modem interface controls, and a sleep mode are all standard features. mcr bit-5 provides a facility for turning off software flow control with any incoming (rx) character. in the 16 mode intsel and mcr bit-3 can be configured to provide a software controlled or continuous interrupt capability. the xr16c864 offers a clock prescaler select pin to allow system/board designers to preset the default baud rate table on power up. the clksel pin selects the div-by-1 or div-by-4 prescaler for the baud rate generator. it can then be overridden following initializatioin by mcr bit-7. the 864 offers several other enhanced features. these features include a chcclk clock input, fstat register, separate irda tx outputs, separate rxrdy and txrdy outputs and a direct memory access interface. the chcclk must be connected to the xtal2 pin for normal operation or to external midi (music instrument digital interface) oscillator for midi applications. a separate register (fstat) is provided for monitoring the real time status of the fifo signals txrdy# and rxrdy# for each of the four uart channels (a-d). separate txrdy and rxrdy outputs for the individual channels are also provided. for infrared applications, four separate irda (infrared data association standard) tx outputs are provided. these outputs are provided in addition to the standard asynchronous modem data outputs. a full direct memory access interface is provided with separate drq lines for rx and tx fifos of the individual channels.
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 9 2.0 functional descriptions 2.1 cpu interface the cpu interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. the 864 data interface supports the intel compatible types of cpus and it is compatible to the industry standard 16c550 uart. no clock (oscillator nor external clock) is required to operate a data bus transaction. each bus cycle is asynchronous using cs# a-d, ior# and iow# or cs#, r/w#, a4 and a3 inputs. all four uart channels share the same data bus for host operations. a typical data bus interconnection for intel and motorola mode is shown in figure 3 . f igure 3. xr16c864/864d t ypical i ntel /m otorola d ata b us i nterconnections vcc vcc dsra# ctsa# rtsa# dtra# rxa txa ria# cda# gnd a0 a1 a2 uart_csa# uart_csb# ior# iow# d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 csa# csb# d0 d1 d2 d3 d4 d5 d6 d7 ior# iow# uart channel a uart channel b uart_intb uart_inta intb inta uart_reset reset serial interface of rs-232 serial interface of rs-232 intel data bus (16 mode) interconnections uart channel c uart channel d similar to ch a similar to ch a similar to ch a uart_intd uart_intc intd intc uart_csc# uart_csd# csc# csd# vcc 16/68# vcc vcc gnd a0 a1 a2 uart_cs# a3 r/w# d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 csa# csb# d0 d1 d2 d3 d4 d5 d6 d7 ior# iow# uart_irq# intb inta reset# serial interface of rs-232 serial interface of rs-232 motorola data bus (68 mode) interconnections vcc uart_reset# (no connect) dsra# ctsa# rtsa# dtra# rxa txa ria# cda# uart channel a uart channel b uart channel c similar to ch a similar to ch a similar to ch a intc (no connect) intd (no connect) a4 csc# csd# vcc 16/68# uart channel d
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 10 2.2 5-volt tolerant inputs for devices that have top mark date code "f2 yyww" and newer, the 864 can accept a voltage of up to 5.5v on any of its inputs (except xtal1) when operating from 2.97v to 5.5v. xtal1 is not 5 volt tolerant. devices that have top mark date code "dc yyww" and older do not have 5v tolerant inputs. 2.3 device reset the reset input resets the internal registers and the serial interface outputs in all four channels to their default state (see ta b l e 1 8 ). an active high pulse of longer than 40 ns duration will be required to activate the reset function in the device. following a power-on reset or an external reset, the 864 is software compatible with previous generation of uarts, 16c454 and 16c554 and 16c654. 2.4 device identification and revision the xr16c864 provides a device identification code and a device revision code to distinguish the part from other devices and revisions. to read the identification code from the part, it is required to set the baud rate generator registers dll and dlm both to 0x00. now reading the content of the dlm will provide 0x14 for the xr16c864 and reading the content of dll will provide the revision of the part; for example, a reading of 0x01 means revision a. 2.5 channel selection the uart provides the user with the capability to bi-directionally transfer information between an external cpu and an external serial communication device. during intel bus mode (16/68# pin is connected to vcc), a logic 0 on chip select pins, csa#, csb#, csc# or csd# allows the user to select uart channel a, b, c or d to configure, send transmit data and/or unload receive data to/from the uart. selecting all four uarts can be useful during power up initialization to write to the same internal registers, but do not attempt to read from all four uarts simultaneously. individual channel select functions are shown in table 1 . during motorola bus mode (16/68# pin is connected to gnd), the package interface pins are configured for connection with motorola, and other popular microprocessor bus types. in this mode the 864 decodes two additional addresses, a3 and a4, to select one of the four uart ports. the a3 and a4 address decode function is used only when in the motorola bus mode. see table 2 . t able 1: c hannel a-d s elect in 16 m ode csa# csb# csc# csd# f unction 1111 uart de-selected 0111 channel a selected 1011 channel b selected 1101 channel c selected 1110 channel d selected 0000 channels a-d selected
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 11 2.6 channels a-d internal registers each uart channel in the 864 has a set of enhanced registers for control, monitoring and data loading and unloading. the configuration register set is compatible to those already available in the standard single 16c550. these registers function as data holding registers (thr/rhr), interrupt status and control registers (isr/ier), a fifo control register (fcr), receive line status and control registers (lsr/lcr), modem status and control registers (msr/mcr), programmable data rate (clock) divisor registers (dll/dlm), and a user accessible scratchpad register (spr). beyond the general 16c550 features and capabilities, the 864 offers enhanced feature registers (emsr, flvl, efr, xon/xoff 1, xon/xoff 2, fctr, trg, fc) that provide automatic rts and cts hardware flow control, xon/xoff software flow control, automatic rs-485 half-duplex direction output enable/disable, fifo trigger level control, and fifo level counters. all the register functions are discussed in full detail later in section 3.0, uart internal registers on page 22 . 2.7 int ouputs for channels a-d the interrupt outputs change according to the operating mode and enhanced features setup. ta b l e 3 and 4 summarize the operating behavior for the transmitter and receiver. also see figure 19 through 23 . t able 2: c hannel a-d s elect in 68 m ode cs# a4 a3 f unction 1 n/a n/a uart de-selected 0 0 0 channel a selected 0 0 1 channel b selected 0 1 0 channel c selected 0 1 1 channel d selected t able 3: int p ins o peration for t ransmitter for c hannels a-d fctr bit-3 fcr b it -0 = 0 (fifo d isabled ) fcr b it -0 = 1 (fifo e nabled ) fcr bit-3 = 0 (dma mode disabled) fcr bit-3 = 1 (dma mode enabled) int pin 0 0 = a byte in thr 1 = thr empty 0 = fifo above trigger level 1 = fifo below trigger level or fifo empty 0 = fifo above trigger level 1 = fifo below trigger level or fifo empty int pin 1 0 = a byte in thr 1 = transmitter empty 0 = fifo above trigger level 1 = fifo below trigger level or transmitter empty 0 = fifo above trigger level 1 = fifo below trigger level or transmitter empty t able 4: int p in o peration for r eceiver for c hannels a-d fcr b it -0 = 0 (fifo d isabled ) fcr b it -0 = 1 (fifo e nabled ) fcr bit-3 = 0 (dma mode disabled) fcr bit-3 = 1 (dma mode enabled) int pin 0 = no data 1 = 1 byte 0 = fifo below trigger level 1 = fifo above trigger level 0 = fifo below trigger level 1 = fifo above trigger level
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 12 2.8 direct memory access in this document, direct memory access will not be referred to by its acronym (dma) to avoid confusion with dma mode (a legacy term) that refers to data block transfer operation. direct memory access mode is enabled via emsr bits 2 and 3. the direct memory access transaction is controlled through the rxdrq [a-d], txdrq [a-d], dack [a-d], aen and tc pins. 2.9 dma mode the dma mode (a legacy term) in this document doesnt mean direct memory access but refers to data block transfer operation. (since the 864 also supports direct memory access, direct memory access will be used instead of dma when explaining direct memory access.) the dma mode affects the state of the rxrdy# a- d and txrdy# a-d output pins. the transmit and receive fifo trigger levels provide additional flexibility to the user for block mode operation. the lsr bits 5-6 provide an indication when the transmitter is empty or has an empty location(s) for more data. the user can optionally operate the transmit and receive fifo in the dma mode (fcr bit-3=1). when the transmit and receive fifo are enabled and the dma mode is disabled (fcr bit-3 = 0), the 864 is placed in single-character mode for data transmit or receive operation. when dma mode is enabled (fcr bit-3 = 1), the user takes advantage of block mode operation by loading or unloading the fifo in a block sequence determined by the programmed trigger level. the following table show their behavior. also see figure 19 through 23 . 2.10 crystal oscillator or external clock input the 864 includes an on-chip oscillator (xtal1 and xtal2) to produce a clock for all four uart sections in the device. the cpu data bus does not require this clock for bus operation. the crystal oscillator provides a system clock to the baud rate generators (brg) section found in each of the uart. xtal1 is the input to the oscillator or external clock buffer input with xtal2 pin being the output. for programming details, see programmable baud rate generator. f igure 4. t ypical oscilator connectionsl the on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10-22 pf capacitance load, esr of 20-120 ohms and 100ppm frequency tolerance) connected externally between the xtal1 and xtal2 pins (see figure 4 ). typical standard crystal t able 5: txrdy# and rxrdy# o utputs in fifo and dma m ode for c hannels a-d p ins fcr bit -0=0 (fifo d isabled ) fcr b it -0=1 (fifo e nabled ) fcr bit-3 = 0 (dma mode disabled) fcr bit-3 = 1 (dma mode enabled) rxrdy# 0 = 1 byte 1 = no data 0 = at least 1 byte in fifo 1 = fifo empty 1 to 0 transition when fifo reaches the trigger level, or timeout occurs. 0 to 1 transition when fifo empties. txrdy# 0 = thr empty 1 = byte in thr 0 = fifo empty 1 = at least 1 byte in fifo 0 = fifo has at least 1 empty location. 1 = fifo is full. c1 22-47pf c2 22-47pf 14.7456 mhz xtal1 xtal2 r=300k to 400k
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 13 frequencies are: 1.8432, 3.6864, 7.3728, 14.7456, 18.432, and 22.1184 mhz. alternatively, an external clock can be connected to the xtal1 pin to clock the internal baud rate generator for standard or custom rates. typical oscillator connections are shown in figure 4 . for further reading on oscillator circuit please see application note dan108 on exars web site. 2.11 programmable baud rate generator each uart has its own baud rate generator (brg) with a prescaler. the prescaler is controlled by a software bit in the mcr register. the mcr register bit-7 sets the prescaler to divide the input crystal or external clock by 1 or 4. the clock output of the prescaler goes to the brg. the brg further divides this clock by a programmable divisor between 1 and (2 16 -1) to obtain a 16x sampling rate clock of the serial data rate. the sampling rate clock is used by the transmitter for data bit shifting and receiver for data sampling. table 6 shows the standard data rates available with a 14.7456 mhz crystal or external clock at 16x sampling rate. when using a non-standard frequency crystal or external clock, the divisor value can be calculated for dll/dlm with the following equation. 2.12 transmitter the transmitter section comprises of an 8-bit transmit shift register (tsr) and 128 bytes of fifo which includes a byte-wide transmit holding register (thr). tsr shifts out every data bit with the 16x internal clock. a bit time is 16 clock periods. the transmitter sends the start-bit followed by the number of data bits, f igure 5. b aud r ate g enerator and p rescaler divisor (decimal) = (xtal1 clock frequency / prescaler) / (serial data rate x 16) t able 6: t ypical data rates with a 14.7456 mh z crystal or external clock o utput data rate mcr bit-7=1 o utput data rate mcr bit-7=0 (d efault ) d ivisor for 16x clock (decimal) d ivisor for 16x clock (hex) dlm p rogram v alue (hex) dll p rogram v alue (hex) d ata r ate e rror (%) 100 600 1200 2400 4800 9600 19.2k 38.4k 57.6k 115.2k 230.4k 400 2400 4800 9600 19.2k 38.4k 76.8k 153.6k 230.4k 460.8k 921.6k 2304 384 192 96 48 24 12 6 4 2 1 900 180 c0 60 30 18 0c 06 04 02 01 09 01 00 00 00 00 00 00 00 00 00 00 80 c0 60 30 18 0c 06 04 02 01 0 0 0 0 0 0 0 0 0 0 0 xtal1 xtal2 crystal osc/ buffer mcr bit-7=0 (default) mcr bit-7=1 dll and dlm registers prescaler divide by 1 prescaler divide by 4 16x sam pling rate clock to transmitter baud rate generator logic
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 14 inserts the proper parity-bit if enabled, and adds the stop-bit(s). the status of the tx fifo and tsr are reported in the line status register (lsr bit-5 and bit-6). 2.12.1 transmit holding register (thr) - write only the transmit holding register is an 8-bit register providing a data interface to the host processor. the host writes transmit data byte to the thr to be converted into a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). the least-significant-bit (bit-0) becomes first data bit to go out. the thr is the input register to the transmit fifo of 128 bytes when fifo operation is enabled by fcr bit-0. every time a write operation is made to the thr, the fifo data pointer is automatically bumped to the next sequential data location. 2.12.2 transmitter operation in non-fifo mode the host loads transmit data to thr one character at a time. the thr empty flag (lsr bit-5) is set when the data byte is transferred to tsr. thr flag can generate a transmit empty interrupt (isr bit-1) when it is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr becomes completely empty. 2.12.3 transmitter operation in fifo mode the host may fill the transmit fifo with up to 128 bytes of transmit data. the thr empty flag (lsr bit-5) is set whenever the tx fifo is empty. the thr empty flag can generate a transmit empty interrupt (isr bit-1) when the fifo becomes empty. the transmit empty interrupt is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr/tx fifo becomes empty. f igure 6. t ransmitter o peration in non -fifo m ode f igure 7. t ransmitter o peration in fifo and f low c ontrol m ode transmit holding register (thr) transmit shift register (tsr) data byte l s b m s b thr interrupt (isr bit-1) enabled by ier bit-1 txnofifo1 16x clock transmit data shift register (tsr) data byte thr interrupt (isr bit-1) falls below the programmed trigger level and then when becomes empty. fifo is enabled by fcr bit-0=1 rx fifo 16x clock auto cts flow control (cts# pin) auto software flow control flow control characters (xoff1/2 and xon1/2 reg. txfifo1 thr
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 15 2.13 receiver the receiver section contains an 8-bit receive shift register (rsr) and 128 bytes of fifo which includes a byte-wide receive holding register (rhr). the rsr uses the 16x clock for timing. it verifies and validates every bit on the incoming character in the middle of each data bit. on the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16x clock rate. after 8 clocks the start bit period should be at the center of the start bit. at this time the start bit is sampled and if it is still a logic 0 it is validated. evaluating the start bit in this manner prevents the receiver from assembling a false character. the rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. if there were any error(s), they are reported in the lsr register bits 2-4. upon unloading the receive data byte from rhr, the receive fifo pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in rhr register. rhr can generate a receive data ready interrupt upon receiving a character or delay until it reaches the fifo trigger level. furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4 word lengths as defined by lcr[1:0] plus 12 bits time. this is equivalent to 3.7-4.6 character times. the rhr interrupt is enabled by ier bit-0. 2.13.1 receive holding register (rhr) - read-only the receive holding register is an 8-bit register that holds a receive data byte from the receive shift register. it provides the receive data interface to the host processor. the rhr register is part of the receive fifo of 128 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in lsr register. when the fifo is enabled by fcr bit-0, the rhr contains the first data character received by the fifo. after the rhr is read, the next character byte is loaded into the rhr and the errors associated with the current data byte are immediately updated in the lsr bits 2-4. f igure 8. r eceiver o peration in non -fifo m ode receive data shift register (rsr) receive data byte and errors rhr interrupt (isr bit-2) receive data holding register (rhr) rxfifo1 16x clock receive data characters data bit validation error tags in lsr bits 4:2
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 16 n ote : table-b selected as trigger table for figure 9 ( ta b l e 1 1 ). 2.14 auto rts hardware flow control automatic rts hardware flow control is used to prevent data overrun to the local receiver fifo. the rts# output is used to request remote unit to suspend/resume data transmission. the auto rts flow control features is enabled to fit specific application requirement (see figure 10 ): enable auto rts flow control using efr bit-6. the auto rts function must be started by asserting rts# output pin (mcr bit-1 to logic 1 after it is enabled). if using the auto rts interrupt: enable rts interrupt through ier bit-6 (after setting efr bit-4). the uart issues an interrupt when the rts# pin makes a transition from low to high: isr bit-5 will be set to logic 1. 2.15 auto rts hysteresis the 864 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with the xr16c850, st16c650a and st16c550 family of uarts. with the auto rts function enabled, an interrupt is generated when the receive fifo reaches the programmed rx trigger level. the rts# pin will not be forced to a logic 1 (rts off), until the receive fifo reaches the upper limit of the hysteresis level. the rts# pin will return to a logic 0 after the rx fifo is unloaded to the lower limit of the hysteresis level. under the above described conditions, the 864 will continue to accept data until the receive fifo gets full. the auto rts function is initiated when the rts# output pin is asserted to a logic 0 (rts on). ta b l e 1 5 shows the complete details for the auto rts# hysteresis levels. please note that this table is for programmable trigger levels only (table d). the hysteresis values for tables a-c are the next higher and next lower trigger levels in tables a-c (see ta b l e 1 1 ). 2.16 auto cts flow control automatic cts flow control is used to prevent data overrun to the remote receiver fifo. the cts# input is monitored to suspend/restart the local transmitter. the auto cts flow control feature is selected to fit specific application requirement (see figure 10 ): enable auto cts flow control using efr bit-7. if using the auto cts interrupt: f igure 9. r eceiver o peration in fifo and a uto rts f low c ontrol m ode receive data shift register (rsr) rxfifo1 16x clock error tags (128-sets) error tags in lsr bits 4:2 128 bytes by 11-bit wide fifo receive data characters fifo trigger=16 example : - rx fifo trigger level selected at 16 bytes (see note below) data fills to 24 data falls to 8 data bit validation receive data fifo receive data receive data byte and errors rhr interrupt (isr bit-2) programmed for desired fifo trigger level. fifo is enabled by fcr bit-0=1 rts# de-asserts when data fills above the flow control trigger level to suspend remote transmitter. enable by efr bit-6=1, mcr bit-1. rts# re-asserts when data falls below the flow control trigger level to restart remote transmitter. enable by efr bit-6=1, mcr bit-1.
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 17 enable cts interrupt through ier bit-7 (after setting efr bit-4). the uart issues an interrupt when the cts# pin is de-asserted (logic 1): isr bit-5 will be set to 1, and uart will suspend transmission as soon as the stop bit of the character in process is shifted out. transmission is resumed after the cts# input is re- asserted (logic 0), indicating more data may be sent. 2.17 auto xon/xoff (software) flow control when software flow control is enabled ( see table 17 ), the 864 compares one or two sequential receive data characters with the programmed xon or xoff-1,2 character value(s). if receive character(s) match the programmed values, the 864 will halt transmission as soon as the current character has completed transmission. when a match occurs, the xoff (if enabled via ier bit-5) flag will be set and the interrupt output pin will be activated. following a suspension due to a match of the xoff character, the 864 will monitor the receive data stream for a match to the xon-1,2 character. if a match is found, the 864 will resume operation and clear the flags (isr bit-4). reset initially sets the contents of the xon/xoff 8-bit flow control registers to a logic 0. following reset the user can write any xon/xoff value desired for software flow control. different conditions can be set to detect xon/ f igure 10. a uto rts and cts f low c ontrol o peration the local uart (uarta) starts data transfer by asserting rtsa# (1). rtsa# is normally connected to ctsb# (2) of remote uart (uartb). ctsb# allows its transmitter to send data (3). txb data arrives and fills uarta receive fifo (4). when rxa data fills up to its receive fifo trigger level, uarta activates its rxa data ready interrupt (5) and con- tinues to receive and put data into its fifo. if interrupt service latency is long and data is not being unloaded, uarta monitors its receive data fill level to match the upper threshold of rts delay and de-assert rtsa# (6). ctsb# follows (7) and request uartb transmitter to suspend data transfer. uartb stops or finishes sending the data bits in its trans- mit shift register (8). when receive fifo data in uarta is unloaded to match the lower threshold of rts delay (9), uarta re-asserts rtsa# (10), ctsb# recognizes the change (11) and restarts its transmitter and data flow again until next receive fifo trigger (12). this same event applies to the reverse direction when uarta sends data to uartb with rtsb# and ctsa# controlling the data flow. rtsa# ctsb# rxa txb transmitter receiver fifo trigger reached auto rts trigger level auto cts monitor rtsa# txb rxa fifo ctsb# remote uart uartb local uart uarta on off on suspend restart rts high threshold data starts on off on assert rts# to begin transmission 1 2 3 4 5 6 7 receive data rts low threshold 9 10 11 receiver fifo trigger reached auto rts trigger level transmitter auto cts monitor rtsb# ctsa# rxb txa inta (rxa fifo interrupt) rx fifo trigger level rx fifo trigger level 8 12 rtscts1
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 18 xoff characters ( see table 17 ) and suspend/resume transmissions. when double 8-bit xon/xoff characters are selected, the 864 compares two consecutive receive characters with two software flow control 8-bit values (xon1, xon2, xoff1, xoff2) and controls tx transmissions accordingly. under the above described flow control mechanisms, flow control characters are not placed (stacked) in the user accessible rx data buffer or fifo. in the event that the receive buffer is overfilling and flow control needs to be executed, the 864 automatically sends an xoff message (when enabled) via the serial tx output to the remote modem. the 864 sends the xoff- 1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate) after the receive fifo crosses the programmed trigger level (for all trigger tables a-d). to clear this condition, the 864 will transmit the programmed xon-1,2 characters as soon as receive fifo is less than one trigger level below the programmed trigger level (for trigger tables a, b, and c) or when receive fifo is less than the trigger level minus the hysteresis value (for trigger table d). this hysteresis value is the same as the auto rts hysteresis value in ta b l e 1 5 . ta b l e 7 below explains this when trigger table-b (see ta b l e 1 1 ) is selected. * after the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2 characters); for example, after 2.083ms has elapsed for 9600 baud and 10-bit word length setting. 2.18 special character detect a special character detect feature is provided to detect an 8-bit character when bit-5 is set in the enhanced feature register (efr). when this character (xoff2) is detected, it will be placed in the fifo along with normal incoming rx data. the 864 compares each incoming receive character with xoff-2 data. if a match exists, the received data will be transferred to fifo and isr bit-4 will be set to indicate detection of special character. although the internal register table shows xon, xoff registers with eight bits of character information, the actual number of bits is dependent on the programmed word length. line control register (lcr) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. the word length selected by lcr bits 0-1 also determines the number of bits that will be used for the special character comparison. bit-0 in the xon, xoff registers corresponds with the lsb bit for the receive character. 2.19 auto rs485 half-duplex control the auto rs485 half-duplex direction control changes the behavior of the transmitter when enabled by fctr bit-3. by default, it de-asserts op1#/rs485 (logic 1) output following the last stop bit of the last character that has been transmitted. this helps in turning around the transceiver to receive the remote stations response. when the host is ready to transmit next polling data packet again, it only has to load data bytes to the transmit fifo. the transmitter automatically re-asserts op1#/rs485 (logic 0) output prior to sending the data. 2.20 infrared mode the 864 uart includes the infrared encoder and decoder compatible to the irda (infrared data association) version 1.0. the irda 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide high- pulse for each 0 bit in the transmit data stream. this signal encoding reduces the on-time of the infrared led, hence reduces the power consumption. see figure 11 below. the infrared encoder and decoder are enabled by setting mcr register bit-6 to a 1. when the infrared feature is enabled, the transmit data output, tx, idles at logic zero level. likewise, the rx input assumes an idle level of logic zero from a reset and power up, see figure 11 . typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the rx pin. each time it senses a light pulse, it returns a logic 1 to the data bit stream. however, this is not true with some t able 7: a uto x on /x off (s oftware ) f low c ontrol rx t rigger l evel int p in a ctivation x off c haracter ( s ) s ent ( characters in rx fifo ) x on c haracter ( s ) s ent ( characters in rx fifo ) 88 8* 0 16 16 16* 8 24 24 24* 16 28 28 28* 24
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 19 infrared modules on the market which indicate a logic 0 by a light pulse. so the 864 has a provision to invert the input polarity to accomodate this. in this case, user can enable fctr bit-2 to invert the input signal. 2.21 sleep mode with auto wake-up the 864 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. all of these conditions must be satisfied for the 864 to enter sleep mode: n no interrupts pending for all four channels of the 864 (isr bit-0 = 1) n sleep mode of all four channels are enabled (ier bit-4 = 1) n modem inputs are not toggling (msr bits 0-3 = 0) n rx input pins are idling at a logic 1 the 864 stops its crystal oscillator to conserve power in the sleep mode. user can check the xtal2 pin for no clock output as an indication that the device has entered the sleep mode. the 864 resumes normal operation by any of the following: n a receive data start bit transition (logic 1 to 0) n a data byte is loaded to the transmitter, thr or fifo n a change of logic state on any of the modem or general purpose serial inputs: cts#, dsr#, cd#, ri# if the 864 is awakened by any one of the above conditions, it will return to the sleep mode automatically after all interrupting conditions have been serviced and cleared. if the 864 is awakened by the modem inputs, a read f igure 11. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding character data bits start stop 0000 0 11 111 bit time 1/16 clock delay irdecoder-1 rx data receive ir pulse (rx pin) character data bits start stop 0000 0 11 111 tx data transmit ir pulse (tx pin) bit time 1/2 bit time 3/16 bit time irencoder-1
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 20 to the msr is required to reset the modem inputs. in any case, the sleep mode will not be entered while an interrupt is pending in any channel. the 864 will stay in the sleep mode of operation until it is disabled by setting ier bit-4 to a logic 0. if the address lines, data bus lines, iow#, ior#, csa#, csb#, csc#, csd# and modem input lines remain steady when the 864 is in sleep mode, the maximum current will be in the microamp range as specified in the dc electrical characteristics on page 40 . if the input lines are floating or are toggling while the 864 is in sleep mode, the current can be up to 100 times more. if any of those signals are toggling or floating, then an external buffer would be required to keep the address, data and control lines steady to achieve the low current. a word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the first few receive characters may be lost. also, make sure the rx input is idling at logic 1 or marking condition during sleep mode. this may not occur when the external interface transceivers (rs-232, rs-485 or another type) are also put to sleep mode and cannot maintain the marking condition. to avoid this, the system design engineer can use a 47k ohm pull-up resistor on the rx a-d inputs. 2.22 internal loopback the 864 uart provides an internal loopback capability for system diagnostic purposes. the internal loopback mode is enabled by setting mcr register bit-4 to logic 1. all regular uart functions operate normally. figure 12 shows how the modem port signals are re-configured. transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending. the tx pin is held at logic 1 or mark condition while rts# and dtr# are de-asserted, and cts#, dsr# cd# and ri# inputs are ignored. caution: the rx input must be held to a logic 1 during loopback test else upon exiting the loopback test the uart may detect and report a false break signal.
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 21 f igure 12. i nternal l oop b ack in c hannels a-d tx a-d rx a-d modem / general purpose control logic internal data bus lines and control signals rts# a-d mcr bit-4=1 vcc vcc transmit shift register (thr/fifo) receive shift register (rhr/fifo) cts# a-d dtr# a-d dsr# a-d rts# cts# dtr# dsr# vcc op1# ri# vcc op2# cd# vcc op1# a-d/rs485 ri# a-d op2# a-d cd# a-d
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 22 3.0 uart internal registers each uart channel in the 864 has its own set of configuration registers selected by address lines a0, a1 and a2 with a specific channel selected (see ta b l e 1 and ta b l e 2 ). the complete register set is shown on ta b l e 8 and ta b l e 9 . t able 8: uart channel a and b uart internal registers a2,a1,a0 a ddresses r egister r ead /w rite c omments 16c550 c ompatible r egisters 0 0 0 rhr - receive holding register thr - transmit holding register read-only write-only lcr[7] = 0 0 0 0 dll - div latch low byte read/write lcr[7] = 1, lcr 1 0xbf 0 0 1 dlm - div latch high byte read/write lcr[7] = 1, lcr 1 0xbf 0 0 0 drev - device revision code read-only dll, dlm = 0x00, lcr[7] = 1, lcr 1 0xbf 0 0 1 dvid - device identification code read-only dll, dlm = 0x00, lcr[7] = 1, lcr 1 0xbf 0 0 1 ier - interrupt enable register read/write lcr[7] = 0 0 1 0 isr - interrupt status register fcr - fifo control register read-only write-only lcr[7] = 0 0 1 1 lcr - line control register read/write 1 0 0 mcr - modem control register read/write lcr[7] = 0 1 0 1 lsr - line status register reserved read-only write-only lcr[7] = 0 1 1 0 msr - modem status register reserved read-only write-only lcr[7] = 0 1 1 1 spr - scratch pad register read/write lcr[7] = 0, fctr[6] = 0 1 1 1 flvl - tx/rx fifo level counter register read-only lcr[7] = 0, fctr[6] = 1 1 1 1 emsr - enhanced mode select register write-only lcr[7] = 0, fctr[6] = 1 e nhanced r egisters 0 0 0 trg - tx/rx fifo trigger level reg fc - tx/rx fifo level counter register write-only read-only lcr = 0xbf 0 0 1 fctr - feature control reg read/write lcr = 0xbf 0 1 0 efr - enhanced function reg read/write lcr = 0xbf 1 0 0 xon-1 - xon character 1 read/write lcr = 0xbf 1 0 1 xon-2 - xon character 2 read/write lcr = 0xbf 1 1 0 xoff-1 - xoff character 1 read/write lcr = 0xbf 1 1 1 xoff-2 - xoff character 2 read/write lcr = 0xbf x x x fstat - fifo status register read-only fsrs# pin is logic 0
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 23 . t able 9: internal registers description. s haded bits are enabled when efr b it -4=1 a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment 16c550 compatible registers 0 0 0 rhr rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 0 0 0 0 thr wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 ier rd/wr 0/ 0/ 0/ 0/ modem stat. int. enable rx line stat. int. enable tx empty int enable rx data int. enable cts# int. enable rts# int. enable xoff int. enable sleep mode enable 0 1 0 isr rd fifos enabled fifos enabled 0/ 0/ int source bit-3 int source bit-2 int source bit-1 int source bit-0 int source bit-5 int source bit-4 0 1 0 fcr wr rx fifo trigger rx fifo trigger 0/ 0/ dma mode enable tx fifo reset rx fifo reset fifos enable tx fifo trigger tx fifo trigger 0 1 1 lcr rd/wr divisor enable set tx break set par- ity even parity parity enable stop bits word length bit-1 word length bit-0 1 0 0 mcr rd/wr 0/ 0/ 0/ internal lopback enable op2#/ int out- put enable op1#/ rs-485 output control rts# output control dtr# output control lcr[7] = 0 brg pres- caler ir mode enable xonany 1 0 1 lsr rd rx fifo global error thr & tsr empty thr empty rx break rx fram- ing error rx parity error rx over- run error rx data ready 1 1 0 msr rd cd# input ri# input dsr# input cts# input delta cd# delta ri# delta dsr# delta cts# 1 1 1 spr rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 0 fctr[6]=0 1 1 1 emsr wr rsvd rsvd auto rts hyst. bit-3 auto rts hyst. bit-2 enable rx dma enable tx dma rx/tx fifo count rx/tx fifo count lcr[7] = 0 fctr[6]=1 1 1 1 flvl rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 24 baud rate generator divisor 0 0 0 dll rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 1 lcr 1 0xbf 0 0 1 dlm rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 0 drev rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 1 lcr 1 0xbf dll=0x00 dlm=0x00 0 0 1 dvid rd 0 0 0 1 0 1 0 0 enhanced registers 0 0 0 trg wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr=0 x bf 0 0 0 fc rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 fctr rd/wr rx/tx mode scpad swap tr i g ta b l e bit-1 tr i g ta b l e bit-0 auto rs485 direction control rx ir input inv. auto rts hyst bit-1 auto rts hyst bit-0 0 1 0 efr rd/wr auto cts# enable auto rts# enable special char select enable ier [7:4], isr [5:4], fcr[5:4], mcr[7:5] soft- ware flow cntl bit-3 soft- ware flow cntl bit-2 soft- ware flow cntl bit-1 soft- ware flow cntl bit-0 1 0 0 xon1 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 xon2 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 0 xoff1 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 1 xoff2 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 x x x fstat rd rx- rdyd# rx- rdyc# rx- rdyb# rx- rdya# tx- rdyd# tx- rdyc# tx- rdyb# tx- rdya# fsrs# pin is a logic 0. no address lines required. t able 9: internal registers description. s haded bits are enabled when efr b it -4=1 a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 25 4.0 internal register descriptions 4.1 receive holding register (rhr) - read- only see receiver on page 15. 4.2 transmit holding register (thr) - write-only see transmitter on page 13. 4.3 interrupt enable register (ier) - read/write the interrupt enable register (ier) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. these interrupts are reported in the interrupt status register (isr). 4.3.1 ier versus receive fifo interrupt mode operation when the receive fifo (fcr bit-0 = 1) and receive interrupts (ier bit-0 = 1) are enabled, the rhr interrupts (see isr bits 2 and 3) status will reflect the following: a. the receive data available interrupts are issued to the host when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. b. fifo level will be reflected in the isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared when the fifo drops below the trigger level. c. the receive data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift register to the receive fifo. it is reset when the fifo is empty. 4.3.2 ier versus receive/transmit fifo polled mode operation when fcr bit-0 equals a logic 1 for fifo enable; resetting ier bits 0-3 enables the xr16c864 in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a. lsr bit-0 indicates there is data in rhr or rx fifo. b. lsr bit-1 indicates an overrun error has occurred and that data in the fifo may not be valid. c. lsr bit 2-4 provides the type of receive data errors encountered for the data byte in rhr, if any. d. lsr bit-5 indicates thr is empty. e. lsr bit-6 indicates when both the transmit fifo and tsr are empty. f. lsr bit-7 indicates a data error in at least one character in the rx fifo. ier[0]: rhr interrupt enable the receive data ready interrupt will be issued when rhr has a data character in the non-fifo mode or when the receive fifo has reached the programmed trigger level in the fifo mode. logic 0 = disable the receive data ready interrupt (default). logic 1 = enable the receiver data ready interrupt. ier[1]: thr interrupt enable this bit enables the transmit ready interrupt which is issued whenever the thr becomes empty in the non- fifo mode or when data in the fifo falls below the programmed trigger level in the fifo mode. if the thr is empty when this bit is enabled, an interrupt will be generated. logic 0 = disable transmit ready interrupt (default). logic 1 = enable transmit ready interrupt. ier[2]: receive line status interrupt enable if any of the lsr register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller about the error status of the current data byte in fifo. these lsr bits generate an interrupt immediately when the character has been received. logic 0 = disable the receiver line status interrupt (default). logic 1 = enable the receiver line status interrupt.
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 26 ier[3]: modem status interrupt enable logic 0 = disable the modem status register interrupt (default). logic 1 = enable the modem status register interrupt. ier[4]: sleep mode enable (requires efr[4] = 1) logic 0 = disable sleep mode (default). logic 1 = enable sleep mode. see sleep mode with auto wake-up on page 19. ier[5]: xoff interrupt enable (requires efr[4]=1) logic 0 = disable the software flow control, receive xoff interrupt (default). logic 1 = enable the software flow control, receive xoff interrupt. see software flow control section for details. ier[6]: rts# output interrupt enable (requires efr[4]=1) logic 0 = disable the rts# interrupt (default). logic 1 = enable the rts# interrupt. the uart issues an interrupt when the rts# pin makes a transition from low to high. ier[7]: cts# input interrupt enable (requires efr[4]=1) logic 0 = disable the cts# interrupt (default). logic 1 = enable the cts# interrupt. the uart issues an interrupt when cts# pin makes a transition from low to high. 4.4 interrupt status register (isr) - read-only the uart provides multiple levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with six interrupt status bits. performing a read cycle on the isr will give the user the current highest pending interrupt level to be serviced, others are queued up to be serviced next. no other interrupts are acknowledged until the pending interrupt is serviced. the interrupt source table, ta b l e 1 0 , shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources associated with each of these interrupt levels. 4.4.1 interrupt generation: lsr is by any of the lsr bits 1, 2, 3 and 4. rxrdy is by rx trigger level. rxrdy time-out is by a 4-char plus 12 bits delay timer. txrdy is by tx trigger level or tx fifo empty (or transmitter empty in auto rs-485 control). msr is by any of the msr bits 0, 1, 2 and 3. receive xoff/special character is by detection of a xoff or special character. cts# is when its transmitter toggles the input pin (from low to high) during auto cts flow control. rts# is when its receiver toggles the output pin (from low to high) during auto rts flow control. 4.4.2 interrupt clearing: lsr interrupt is cleared by a read to the lsr register. rxrdy interrupt is cleared by reading data until fifo falls below the trigger level. rxrdy time-out interrupt is cleared by reading rhr. txrdy interrupt is cleared by a read to the isr register or writing to thr. msr interrupt is cleared by a read to the msr register. xoff interrupt is cleared by a read to isr or when xon character(s) is received. special character interrupt is cleared by a read to isr or after the next character is received. rts# and cts# flow control interrupts are cleared by a read to the msr register.
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 27 ] isr[0]: interrupt status logic 0 = an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine. logic 1 = no interrupt pending (default condition). isr[3:1]: interrupt status these bits indicate the source for a pending interrupt at interrupt priority levels (see interrupt source table 10). isr[5:4]: interrupt status these bits are enabled when efr bit-4 is set to a logic 1. isr bit-4 indicates that the receiver detected a data match of the xoff character(s). note that once set to a logic 1, the isr bit-4 will stay a logic 1 until a xon character is received. isr bit-5 indicates that cts# or rts# has changed state. isr[7:6]: fifo enable status these bits are set to a logic 0 when the fifos are disabled. they are set to a logic 1 when the fifos are enabled. 4.5 fifo control register (fcr) - write-only this register is used to enable the fifos, clear the fifos, set the transmit/receive fifo trigger levels, and select the dma mode. the dma and fifo modes are defined as follows: fcr[0]: tx and rx fifo enable logic 0 = disable the transmit and receive fifo (default). logic 1 = enable the transmit and receive fifos. this bit must be set to logic 1 when other fcr bits are written or they will not be programmed. fcr[1]: rx fifo reset this bit is only active when fcr bit-0 is a 1. logic 0 = no receive fifo reset (default) logic 1 = reset the receive fifo pointers and fifo level counter logic (the receive shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. t able 10: i nterrupt s ource and p riority l evel p riority isr r egister s tatus b its s ource of interrupt l evel b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 1 0 0 0 1 1 0 lsr (receiver line status register) 2 0 0 1 1 0 0 rxrdy (receive data time-out) 3 0 0 0 1 0 0 rxrdy (received data ready) 4 0 0 0 0 1 0 txrdy (transmit ready) 5 0 0 0 0 0 0 msr (modem status register) 6 0 1 0 0 0 0 rxrdy (received xoff or special character) 7 1 0 0 0 0 0 cts#, rts# change of state - 0 0 0 0 0 1 none (default)
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 28 fcr[2]: tx fifo reset this bit is only active when fcr bit-0 is a 1. logic 0 = no transmit fifo reset (default). logic 1 = reset the transmit fifo pointers and fifo level counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[3]: dma mode select controls the behavior of the txrdy# and rxrdy# pins. see dma operation section for details. logic 0 = normal operation (default). logic 1 = dma mode. fcr[5:4]: transmit fifo trigger select (logic 0 = default, tx trigger level = one) these 2 bits set the trigger level for the transmit fifo. the uart will issue a transmit interrupt when the number of characters in the fifo falls below the selected trigger level, or when it gets empty in case that the fifo did not get filled over the trigger level on last re-load. ta b l e 1 1 below shows the selections. efr bit-4 must be set to 1 before these bits can be accessed. note that the receiver and the transmitter cannot use different trigger tables. whichever selection is made last applies to both the rx and tx side. fcr[7:6]: receive fifo trigger select (logic 0 = default, rx trigger level =1) the fctr bits 5-4 are associated with these 2 bits. these 2 bits are used to set the trigger level for the receive fifo. the uart will issue a receive interrupt when the number of the characters in the fifo crosses the trigger level. ta b l e 1 1 shows the complete selections. note that the receiver and the transmitter cannot use different trigger tables. whichever selection is made last applies to both the rx and tx side.
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 29 4.6 line control register (lcr) - read/write the line control register is used to specify the asynchronous data communication format. the word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr[1:0]: tx and rx word length select these two bits specify the word length to be transmitted or received. t able 11: t ransmit and r eceive fifo t rigger l evel s election fctr b it -5 fctr b it -4 fcr b it -7 fcr b it -6 fcr b it -5 fcr bit -4 r eceive t rigger l evel t ransmit t rigger l evel c ompatibility 00 0 0 1 1 0 1 0 1 00 1 (default) 4 8 14 1 (default) table-a. 16c550, 16c2550, 16c2552, 16c554, 16c580 compatible. 01 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 8 16 24 28 16 8 24 30 table-b. 16c650a compatible. 10 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 8 16 56 60 8 16 32 56 table-c. 16c654 compatible. 1 1xxxxprogrammable via trg register. fctr[7] = 0. programmable via trg register. fctr[7] = 1. table-d. 16l2750, 16c2850, 16c2852, 16c850, 16c864 compatible. bit-1 bit-0 w ord length 0 0 5 (default) 01 6 10 7 11 8
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 30 lcr[2]: tx and rx stop-bit length select the length of stop bit is specified by this bit in conjunction with the programmed word length. lcr[3]: tx and rx parity select parity or no parity can be selected via this bit. the parity bit is a simple way used in communications for data integrity check. see ta b l e 1 2 for parity selection summary below. logic 0 = no parity. logic 1 = a parity bit is generated during the transmission while the receiver checks for parity error of the data character received. lcr[4]: tx and rx parity select if the parity bit is enabled with lcr bit-3 set to a logic 1, lcr bit-4 selects the even or odd parity format. logic 0 = odd parity is generated by forcing an odd number of logic 1s in the transmitted character. the receiver must be programmed to check the same format (default). logic 1 = even parity is generated by forcing an even number of logic 1s in the transmitted character. the receiver must be programmed to check the same format. lcr[5]: tx and rx parity select if the parity bit is enabled, lcr bit-5 selects the forced parity format. lcr bit-5 = logic 0, parity is not forced (default). lcr bit-5 = logic 1 and lcr bit-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. lcr bit-5 = logic 1 and lcr bit-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. lcr[6]: transmit break enable when enabled, the break control bit causes a break condition to be transmitted (the tx output is forced to a space, logic 0, state). this condition remains, until disabled by setting lcr bit-6 to a logic 0. logic 0 = no tx break condition (default). logic 1 = forces the transmitter output (tx) to a space, logic 0, for alerting the remote receiver of a line break condition. bit-2 w ord length s top bit length (b it time ( s )) 0 5,6,7,8 1 (default) 15 1-1/2 1 6,7,8 2 t able 12: p arity selection lcr b it -5 lcr b it -4 lcr b it -3 p arity selection xx 0 no parity 0 0 1 odd parity 01 1 even parity 1 0 1 force parity to mark, 1 1 1 1 forced parity to space, 0
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 31 lcr[7]: baud rate divisors enable logic 0 = data registers are selected (default). logic 1 = divisor latch registers are selected. 4.7 modem control register (mcr) or general purpose outputs control - read/write the mcr register is used for controlling the serial/modem interface signals or general purpose inputs/outputs. mcr[0]: dtr# output the dtr# pin is a modem control output. if the modem interface is not used, this output may be used as a general purpose output. logic 0 = force dtr# output to a logic 1 (default). logic 1 = force dtr# output to a logic 0. mcr[1]: rts# output the rts# pin is a modem control output and may be used for automatic hardware flow control by enabled by efr bit-6. if the modem interface is not used, this output may be used as a general purpose output. logic 0 = force rts# output to a logic 1 (default). logic 1 = force rts# output to a logic 0. mcr[2]: op1# output or rs485 output control in the loopback mode, this bit is used to write the state of the modem ri# interface signal. if auto rs-485 half-duplex direction control is enabled via fctr bit-3, mcr bit-2 should not be written to. mcr[3]: int output enable enable or disable int outputs to become active or in three-state. this function is associated with the intsel input, see below table for details. this bit is also used to control the op2# signal during internal loopback mode. intsel pin must be set to a logic zero during 68 mode. logic 0 = int (a-d) outputs disabled (three state) in the 16 mode (default). during loopback mode, it sets op2# internally to a logic 1. logic 1 = int (a-d) outputs enabled (active) in the 16 mode. during loopback mode, it sets op2# internally to a logic 0. mcr[4]: internal loopback enable logic 0 = disable loopback mode (default). logic 1 = enable local loopback mode, see loopback section and figure 12 . mcr[5]: xon-any enable logic 0 = disable xon-any function (for 16c550 compatibility, default). logic 1 = enable xon-any function. in this mode, any rx character received will resume transmit operation. the rx character will be loaded into the rx fifo , unless the rx character is an xon or xoff character and the 864 is programmed to use the xon/xoff flow control. t able 13: int o utput m odes intsel p in mcr b it -3 int a-d o utputs in 16 m ode 0 0 three-state 01 active 1x active
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 32 mcr[6]: infrared encoder/decoder enable logic 0 = enable the standard modem receive and transmit input/output interface (default). logic 1 = enable infrared irda receive and transmit inputs/outputs. the tx/rx output/input are routed to the infrared encoder/decoder. the data input and output levels conform to the irda infrared interface requirement. the rx fifo may need to be flushed upon enable. while in this mode, the infrared tx output will be a logic 0 during idle data conditions. mcr[7]: clock prescaler select the clksel pin selects this function upon power up or reset. after the power up or reset, this register bit will have control and can alter the logic state. logic 0 = divide by one. the input clock from the crystal or external clock is fed directly to the programmable baud rate generator without further modification, i.e., divide by one (default). logic 1 = divide by four. the prescaler divides the input clock from the crystal or external clock by four and feeds it to the programmable baud rate generator, hence, data rates become one forth. 4.8 line status register (lsr) - read only this register provides the status of data transfers between the uart and the host. if lsr bits 1-4 are asserted, an interrupt will be generated immediately if ier bit-2 is enabled. lsr[0]: receive data ready indicator logic 0 = no data in receive holding register or fifo (default). logic 1 = data has been received and is saved in the receive holding register or fifo. lsr[1]: receiver overrun flag logic 0 = no overrun error (default). logic 1 = overrun error. a data overrun error condition occurred in the receive shift register. this happens when additional data arrives while the fifo is full. in this case the previous data in the receive shift register is overwritten. note that under this condition the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the error. lsr[2]: receive data parity error tag logic 0 = no parity error (default). logic 1 = parity error. the receive character in rhr does not have correct parity information and is suspect. this error is associated with the character available for reading in rhr. lsr[3]: receive data framing error tag logic 0 = no framing error (default). logic 1 = framing error. the receive character did not have a valid stop bit(s). this error is associated with the character available for reading in rhr. lsr[4]: receive break tag logic 0 = no break condition (default). logic 1 = the receiver received a break signal (rx was a logic 0 for at least one character frame time). in the fifo mode, only one break character is loaded into the fifo. the break indication remains until the rx input returns to the idle condition, mark or logic 1. lsr[5]: transmit holding register empty flag this bit is the transmit holding register empty indicator. the thr bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to the transmit shift register. the bit is reset to logic 0 concurrently with the data loading to the transmit holding register by the host. in the fifo mode this bit is set when the transmit fifo is empty, it is cleared when the transmit fifo contains at least 1 byte.
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 33 lsr[6]: thr and tsr empty flag this bit is set to a logic 1 whenever the transmitter goes idle. it is set to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bit is set to a logic 1 whenever the transmit fifo and transmit shift register are both empty. lsr[7]: receive fifo data error flag logic 0 = no fifo error (default). logic 1 = a global indicator for the sum of all error bits in the rx fifo. at least one parity error, framing error or break indication is in the fifo data. this bit clears when there is no more error(s) in any of the bytes in the rx fifo. 4.9 modem status register (msr) - read only this register provides the current state of the modem interface input signals. lower four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a signal from the modem changes state. these bits may be used for general purpose inputs when they are not used with modem signals. msr[0]: delta cts# input flag logic 0 = no change on cts# input (default). logic 1 = the cts# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3). msr[1]: delta dsr# input flag logic 0 = no change on dsr# input (default). logic 1 = the dsr# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3). msr[2]: delta ri# input flag logic 0 = no change on ri# input (default). logic 1 = the ri# input has changed from a logic 0 to a logic 1, ending of the ringing signal. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3). msr[3]: delta cd# input flag logic 0 = no change on cd# input (default). logic 1 = indicates that the cd# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3). msr[4]: cts input status cts# pin may function as automatic hardware flow control signal input if it is enabled and selected by auto cts (efr bit-7). auto cts flow control allows starting and stopping of local data transmissions based on the modem cts# signal. a logic 1 on the cts# pin will stop uart transmitter as soon as the current character has finished transmission, and a logic 0 will resume data transmission. normally msr bit-4 bit is the compliment of the cts# input. however in the loopback mode, this bit is equivalent to the rts# bit in the mcr register. the cts# input may be used as a general purpose input when the modem interface is not used. msr[5]: dsr input status dsr# (active high, logical 1). normally this bit is the compliment of the dsr# input. in the loopback mode, this bit is equivalent to the dtr# bit in the mcr register. the dsr# input may be used as a general purpose input when the modem interface is not used. msr[6]: ri input status ri# (active high, logical 1). normally this bit is the compliment of the ri# input. in the loopback mode this bit is equivalent to bit-2 in the mcr register. the ri# input may be used as a general purpose input when the modem interface is not used.
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 34 msr[7]: cd input status cd# (active high, logical 1). normally this bit is the compliment of the cd# input. in the loopback mode this bit is equivalent to bit-3 in the mcr register. the cd# input may be used as a general purpose input when the modem interface is not used. 4.10 scratch pad register (spr) - read/write this is a 8-bit general purpose register for the user to store temporary data. the content of this register is preserved during sleep mode but becomes 0xff (default) after a reset or a power off-on cycle. 4.11 enhanced mode select register (emsr) this register replaces spr (during a write) and is accessible only when fctr[6] = 1. emsr[1:0]: receive/transmit fifo count (write-only) when scratchpad swap (fctr[6]) is asserted, emsr bits 1-0 controls what mode the fifo level counter is operating in. during alternate rx/tx fifo counter mode, the first value read after emsr bits 1-0 have been asserted will always be the rx fifo counter. the second value read will correspond with the tx fifo counter. the next value will be the rx fifo counter again, then the tx fifo counter and so on and so forth. emsr[2]: transmit direct memory access request enable logic 0 = normal. logic 1 = enable tx direct memory access request. see dack, tc, aen, txdrq and rxdrq pin descriptions for details. emsr[3]: receive direct memory access request enable logic 0 = normal. logic 1 = enable rx direct memory access request. see dack, tc, aen, txdrq and rxdrq pin descriptions for details. t able 14: s cratchpad s wap s election fctr[6] emsr[1] emsr[0] scratchpad is 0 x x scratchpad 1 0 0 rx fifo counter mode 1 0 1 tx fifo counter mode 1 1 0 rx fifo counter mode 1 1 1 alternate rx/tx fifo counter mode
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 35 emsr[5:4]: extended rts hysteresis t able 15: a uto rts h ysteresis emsr[7:6]: reserved 4.12 fifo level register (flvl) - read-only the fifo level register replaces the scratchpad register (during a read) when fctr[6] = 1. note that this is not identical to the fifo data count register which can be accessed when lcr = 0xbf. flvl[7:0]: fifo level register this register provides the fifo counter level for the rx fifo or the tx fifo or both depending on emsr[1:0]. see table 14 for details. 4.13 baud rate generator registers (dll and dlm) - read/write the concatenation of the contents of dlm and dll gives the 16-bit divisor value which is used to calculate the baud rate: baud rate = (clock frequency / 16) / divisor see mcr bit-7 and the baud rate table also. 4.14 device identification register (dvid) - read only this register contains the device id (0x14 for xr16c864). prior to reading this register, dll and dlm should be set to 0x00. 4.15 device revision register (drev) - read only this register contains the device revision information. for example, 0x01 means revision a. prior to reading this register, dll and dlm should be set to 0x00. 4.16 trigger level (trg) - write-only user programmable transmit/receive trigger level register. trg[7:0]: trigger level register these bits are used to program desired trigger levels when trigger table-d is selected. fctr bit-7 selects between programming the rx trigger level (a logic 0) and the tx trigger level (a logic 1). emsr b it -5 emsr b it -4 fctr b it -1 fctr b it -0 rts# h ysteresis (c haracters ) 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 4 6 8 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 8 16 24 32 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 40 44 48 52 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 12 20 28 36
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 36 4.17 fifo data count register (fc) - read-only this register is accessible when lcr = 0xbf. note that this register is not identical to the fifo level count register which is located in the general register set when fctr bit-6 = 1 (scratchpad register swap). it is suggested to read the fifo level count register at the scratchpad register location when fctr bit-6 = 1. see ta b l e 1 4 . fc[7:0]: fifo data count register transmit/receive fifo count. number of characters in transmit (fctr[7] = 1) or receive fifo (fctr[7] = 0) can be read via this register. 4.18 feature control register (fctr) - read/write this register controls the xr16c864 new functions that are not available in st16c554 or st16c654. fctr[1:0]: rts hysteresis user selectable rts# hysteresis levels for hardware flow control application. after reset, these bits are set to 0 to select the next trigger level for hardware flow control. see ta b l e 1 5 for more details. fctr[2]: irda rx inversion logic 0 = select rx input as encoded irda data (idle state will be logic 0). logic 1 = select rx input as inverted encoded irda data (idle state will be logic 1). fctr[3]: auto rs-485 direction control logic 0 = op1# can be used as a general purpose output and can be controlled via mcr bit-2. logic 1 = op1# is used as the auto rs-485 half-duplex direction control output. the tx ready interrupt behavior also changes. see ta b l e 3 . fctr[5:4]: transmit/receive trigger table select see ta b l e 1 1 for more details. fctr[6]: scratchpad swap logic 0 = scratch pad register is selected as general read and write register. st16c550 compatible mode. logic 1 = fifo count register (read-only), enhanced mode select register (write-only). number of characters in transmit or receive holding register can be read via scratch pad register when this bit is set. enhanced mode select register is selected when it is written into. fctr[7]: programmable trigger register select logic 0 = registers trg and fc selected for rx. logic 1 = registers trg and fc selected for tx. 4.19 enhanced feature register (efr) - read/write enhanced features are enabled or disabled using this register. bit 0-3 provide single or dual consecutive character software flow control selection (see ta b l e 1 7 ). when the xon1 and xon2 and xoff1 and xoff2 modes are selected, the double 8-bit words are concatenated into two sequential characters. caution: note that whenever changing the tx or rx flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting. t able 16: t rigger t able s elect fctr b it -5 fctr b it -4 t able 0 0 table-a (tx/rx) 0 1 table-b (tx/rx) 1 0 table-c (tx/rx) 1 1 table-d (tx/rx)
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 37 efr[3:0]: software flow control select single character and dual sequential characters software flow control is supported. combinations of software flow control can be selected by programming these bits. efr[4]: enhanced function bits enable enhanced function control bit. this bit enables ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 to be modified. after modifying any enhanced bits, efr bit-4 can be set to a logic 0 to latch the new values. this feature prevents legacy software from altering or overwriting the enhanced functions once set. normally, it is recommended to leave it enabled, logic 1. logic 0 = modification disable/latch enhanced features. ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 are saved to retain the user settings. after a reset, the ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7are set to a logic 0 to be compatible with st16c550 mode (default). logic 1 = enables the above-mentioned register bits to be modified by the user. efr[5]: special character detect enable logic 0 = special character detect disabled (default). logic 1 = special character detect enabled. the uart compares each incoming receive character with data in xoff-2 register. if a match exists, the receive data will be transferred to fifo and isr bit-4 will be set to indicate detection of the special character. bit-0 corresponds with the lsb bit of the receive character. if flow control is set for comparing xon1, xoff1 (efr [1:0]= 10) then flow control and special character work normally. however, if flow control is set for comparing xon2, xoff2 (efr[1:0]= 01) then flow control works normally, but xoff2 will not go to the fifo, and will generate an xoff interrupt and a special character interrupt, if enabled via ier bit-5. t able 17: s oftware f low c ontrol f unctions efr bit -3 c ont -3 efr bit -2 c ont -2 efr bit -1 c ont -1 efr bit -0 c ont -0 t ransmit and r eceive s oftware f low c ontrol 0 0 0 0 no tx and rx flow control (default and reset) 0 0 x x no transmit flow control 1 0 x x transmit xon1, xoff1 0 1 x x transmit xon2, xoff2 1 1 x x transmit xon1 and xon2, xoff1 and xoff2 x x 0 0 no receive flow control x x 1 0 receiver compares xon1, xoff1 x x 0 1 receiver compares xon2, xoff2 1 0 1 1 transmit xon1, xoff1 receiver compares xon1 or xon2, xoff1 or xoff2 0 1 1 1 transmit xon2, xoff2 receiver compares xon1 or xon2, xoff1 or xoff2 1 1 1 1 transmit xon1 and xon2, xoff1 and xoff2, receiver compares xon1 and xon2, xoff1 and xoff2 0 0 1 1 no transmit flow control, receiver compares xon1 and xon2, xoff1 and xoff2
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 38 efr[6]: auto rts flow control enable rts# output may be used for hardware flow control by setting efr bit-6 to logic 1. when auto rts is selected, an interrupt will be generated when the receive fifo is filled to the programmed trigger level and rts de-asserts to a logic 1 at the next upper trigger level/hysteresis level. rts# will return to a logic 0 when fifo data falls below the next lower trigger level/hysteresis level. the rts# output must be asserted (logic 0) before the auto rts can take effect. rts# pin will function as a general purpose output when hardware flow control is disabled. logic 0 = automatic rts flow control is disabled (default). logic 1 = enable automatic rts flow control. efr[7]: auto cts flow control enable automatic cts flow control. logic 0 = automatic cts flow control is disabled (default). logic 1 = enable automatic cts flow control. data transmission stops when cts# input de-asserts to logic 1. data transmission resumes when cts# returns to a logic 0. 4.20 software flow control registers (xoff1, xoff2, xon1, xon2) - read/write these registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2. for more details, see ta b l e 7 . 4.21 fifo status register (fstat) - read/write the fifo status register provides a status indication for each of the transmit and receive fifo. these status bits contain the inverted logic states of the txrdy# a-d outputs and the (un-inverted) logic states of the rxrdy# a-d outputs. the contents of the fstat register are placed on the data bus when the fsrs# pin (pin 76) is a logic 0. also see fsrs# pin description. fstat[3:0]: txrdy# a-d status bits please see ta b l e 5 for the interpretation of the txrdy# signals. fstat[7:4]: rxrdy# a-d status bits please see ta b l e 5 for the interpretation of the rxrdy# signals.
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 39 t able 18: uart reset conditions for channels a-d registers reset state dll bits 7-0 = 0xxx dlm bits 7-0 = 0xxx rhr bits 7-0 = 0xxx thr bits 7-0 = 0xxx ier bits 7-0 = 0x00 fcr bits 7-0 = 0x00 isr bits 7-0 = 0x01 lcr bits 7-0 = 0x00 mcr bits 7-0 = 0x00 lsr bits 7-0 = 0x60 msr bits 3-0 = logic 0 bits 7-4 = logic levels of the inputs inverted spr bits 7-0 = 0xff emsr bits 7-0 = 0x00 flvl bits 7-0 = 0x00 trg bits 7-0 = 0x00 fc bits 7-0 = 0x00 fctr bits 7-0 = 0x00 efr bits 7-0 = 0x00 xon1 bits 7-0 = 0x00 xon2 bits 7-0 = 0x00 xoff1 bits 7-0 = 0x00 xoff2 bits 7-0 = 0x00 fstat bits 7-0 = 0xff i/o signals reset state tx logic 1 irtx logic 0 rts# logic 1 dtr# logic 1 rxrdy# logic 1 txrdy# logic 0 int xr16c864 = three-state condition xr16c864d = logic 0 irq# logic 1 (68 mode, intsel = 0)
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 40 electrical characteristics test 1: the following inputs remain steady at vcc or gnd state to minimize sleep current: a0-a2, d0-d7, ior#, iow#, csa#, csb#, csc#, and csd#. also, rxa, rxb, rxc, and rxd inputs idle at logic 1 state while asleep. absolute maximum ratings power supply range 7 volts voltage at any pin gnd-0.3 v to 7 v operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c package dissipation 500 mw typical package thermal resistance data (margin of error: 15%) thermal resistance (100-qfp) theta-ja = 45 o c/w, theta-jc = 12 o c/w dc electrical characteristics u nless otherwise noted : ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.97 to 5.5v s ymbol p arameter l imits 3.3v m in m ax l imits 5.0v m in m ax u nits c onditions v ilck clock input low level -0.3 0.6 -0.5 0.6 v v ihck clock input high level 2.4 vcc 3.0 vcc v v il input low voltage -0.3 0.8 -0.5 0.8 v v ih input high voltage (devices with top mark date code of "dc yyww" and older) 2.0 vcc 2.2 vcc v v ih input high voltage (devices with top mark date code of "f2 yyww" and newer) 2.0 5.5 2.2 5.5 v v ol output low voltage 0.4 0.4 v i ol = 6 ma i ol = 4 ma v oh output high voltage 2.0 2.4 v i oh = -6 ma i oh = -1 ma i il input low leakage current 10 10 ua i ih input high leakage current 10 10 ua c in input pin capacitance 5 5 pf i cc power supply current 3 6 ma i sleep sleep current 100 200 ua see test 1
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 41 ac electrical characteristics ta = 0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.97 to 5.5v s ymbol p arameter l imits 3.3 m in m ax l imits 5.0 m in m ax u nit c onditions clk clock pulse duration 20 15 ns osc oscillator frequency 8 24 mhz osc external clock frequency 24 32 mhz t as address setup time (16 mode) 10 5 ns t ah address hold time (16 mode) 10 5 ns t cs chip select width (16 mode) 66 50 ns trd ior# strobe width (16 mode) 35 25 ns tdy read cycle delay (16 mode) 40 30 ns trdv data access time (16 mode) 35 25 ns tdd data disable time (16 mode) 0 25 0 15 ns twr iow# strobe width (16 mode) 35 25 ns tdy write cycle delay (16 mode) 40 30 ns tds data setup time (16 mode) 10 5 ns tdh data hold time (16 mode) 10 5 ns t ads address setup (68 mode) 10 10 ns t adh address hold (68 mode) 15 15 ns trws r/w# setup to cs# (68 mode) 10 5 ns t rda read data access (68 mode) 15 15 ns trdh read data hold (68 mode) 15 15 ns t wds write data setup (68 mode) 20 15 ns t wdh write data hold (68 mode) 10 10 ns trwh cs# de-asserted to r/w# de-asserted (68 mode) 10 10 ns tcsl cs# strobe width (68 mode) 40 40 ns tcsd cs# cycle delay (68 mode) 70 70 ns twdo delay from iow# to output 50 40 ns 100 pf load tmod delay to set interrupt from modem input 40 35 ns 100 pf load trsi delay to reset interrupt from ior# 40 35 ns 100 pf load tssi delay from stop to set interrupt 1 1 bclk trri delay from ior# to reset interrupt 40 40 ns 100 pf load
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 42 tsi delay from stop to interrupt 45 40 ns tint delay from initial int reset to transmit start 8 24 8 24 bclk twri delay from iow# to reset interrupt 45 40 ns tssr delay from stop to set rxrdy# 1 1 bclk trr delay from ior# to reset rxrdy# 45 40 ns twt delay from iow# to set txrdy# 45 40 ns tsrt delay from center of start to reset txrdy# 8 8 bclk trst reset pulse width 40 40 ns n baud rate divisor 1 2 16 -1 1 2 16 -1 - bclk baud clock 16x of data rate bps f igure 13. c lock t iming f igure 14. m odem i nput /o utput t iming f or c hannels a-d ac electrical characteristics ta = 0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.97 to 5.5v s ymbol p arameter l imits 3.3 m in m ax l imits 5.0 m in m ax u nit c onditions osc clk clk external clock io w # io w rts# dtr# cd# cts# dsr# in t io r # ri# t wdo t mod t mod t rsi t mod active active change of state change of state active active active change of state change of state change of state active active
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 43 f igure 15. 16 m ode (i ntel ) d ata b us r ead t iming for c hannels a-d f igure 16. 16 m ode (i ntel ) d ata b us w rite t iming for c hannels a-d t as t dd t ah t rd t rdv t dy t dd t rdv t ah t as t cs valid address valid address valid data valid data a0-a7 cs# ior# d0-d7 rdtm t cs t rd 16write t as t dh t ah t wr t ds t dy t dh t ds t ah t as t cs valid address valid address valid data valid data a0-a7 cs# iow# d0-d7 t cs t wr
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 44 f igure 17. 68 m ode (m otorola ) d ata b us r ead t iming for c hannels a-d f igure 18. 68 m ode (m otorola ) d ata b us w rite t iming for c hannels a-d 68read t ads t rdh t adh t csl t rda t csd t rws valid address valid address valid data a0-a7 cs# r/w# d0-d7 t rwh valid data 68write t ads t adh t csl t wds t csd t rws valid address valid address valid data a0-a7 cs# r/w# d0-d7 t rwh valid data t wdh
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 45 f igure 19. r eceive r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a-d f igure 20. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a-d rx rxrdy# ior# int d0:d7 start bit d0:d7 stop bit d0:d7 t ssr 1 byte in rhr active data ready active data ready active data ready 1 byte in rhr 1 byte in rhr t ssr t ssr rxnfm t rr t rr t rr t ssr t ssr t ssr (reading data out of rhr) tx txrdy# iow# int* d0:d7 start bit d0:d7 stop bit d0:d7 t wt txnonfifo t wt t wt t wri t wri t wri t srt t srt t srt *int is cleared when the isr is read or when data is loaded into the thr. isr is read isr is read isr is read (loading data into thr) (unloading) ier[1] enabled
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 46 f igure 21. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ] for c hannels a-d f igure 22. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ] for c hannels a-d rx rxrdy# ior# int d0:d7 s t ssr rxintdma# rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties first byte is received in rx fifo d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo) rx rxrdy# ior# int d0:d7 s t ssr rxfifodma rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo)
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 47 f igure 23. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] for c hannels a-d tx txrdy# iow# int* txdma# d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t wri (unloading) (loading data into fifo) last data byte transmitted tx fifo fills up to trigger level tx fifo drops below trigger level data in tx fifo tx fifo empty t wt t srt tx fifo empty t t s t si isr is read ier[1] enabled isr is read *int is cleared when the isr is read or when tx fifo fills up to the trigger level.
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 48 package dimensions 100 lead plastic quad flat pack (14 mm x 20 mm qfp, 1.95 mm form) note: the control dimension is the millimeter column inches millimeters symbol min max min max a 0.102 0.134 2.60 3.40 a1 0.002 0.014 0.05 0.35 a2 0.100 0.120 2.55 3.05 b 0.009 0.015 0.22 0.38 c 0.004 0.009 0.11 0.23 d 0.931 0.951 23.65 24.15 d1 0.783 0.791 19.90 20.10 e 0.695 0.715 17.65 18.15 e1 0.547 0.555 13.90 14.10 e 0.0256 bsc 0.65 bsc l 0.029 0.040 0.73 1.03 a 0 7 0 7 80 51 50 31 130 81 100 d d 1 e e 1 b e a 2 a a 1 a seating plane l c p
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 49 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2004 exar corporation datasheet april 2004. send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. revision history d ate r evision d escription january 2004 rev. 2.0 added revision history. changed to standard style format. clarified sleep mode conditions. renamed fifordy register to fstat register. devices with top mark date code of "f2 yyww" and newer have 5v toler- ant inputs (except for xtal1). devices with top mark date code of "dc yyww" and older do not have 5v tolerant inputs. april 2004 rev. 2.0.1 updated fctr bit-3 description.
xr16c864 ? ? ? ? 2.97v to 5.5v quad uart with 128-byte fifo rev. 2.0.1 1 table of contents general description .................................................................................................1 f eatures ............................................................................................................................... ......................1 a pplications ............................................................................................................................... .................1 f igure 1. xr16c864 b lock d iagram ............................................................................................................................... ............ 1 f igure 2. xr16c864 p in o ut a ssignment i n 16 and 68 m ode ................................................................................................... 2 pin descriptions .........................................................................................................3 ordering information ............................................................................................................................... ..3 1.0 product description ..................................................................................................... ................8 2.0 functional descriptions ................................................................................................. ............9 2.1 cpu interface ........................................................................................................... ................................... 9 f igure 3. xr16c864/864d t ypical i ntel /m otorola d ata b us i nterconnections ................................................................... 9 2.2 5-volt tolerant inputs .................................................................................................. ....................... 10 2.3 device reset ............................................................................................................ .................................. 10 2.4 device identification and revision ...................................................................................... ............. 10 2.5 channel selection ....................................................................................................... ........................... 10 t able 1: c hannel a-d s elect in 16 m ode ............................................................................................................................... .. 10 2.6 channels a-d internal registers ......................................................................................... ........... 11 2.7 int ouputs for channels a-d ............................................................................................. ................. 11 t able 2: c hannel a-d s elect in 68 m ode ............................................................................................................................... .. 11 t able 3: int p ins o peration for t ransmitter for c hannels a-d ......................................................................................... 11 t able 4: int p in o peration for r eceiver for c hannels a-d ................................................................................................. 11 2.8 direct memory access .................................................................................................... ...................... 12 2.9 dma mode ................................................................................................................ ..................................... 12 2.10 crystal oscillator or external clock input ......................................................................... 12 f igure 4. t ypical oscilator connectionsl ............................................................................................................................... 12 t able 5: txrdy# and rxrdy# o utputs in fifo and dma m ode for c hannels a-d ........................................................... 12 2.11 programmable baud rate generator ....................................................................................... .. 13 2.12 transmitter ............................................................................................................ ................................. 13 f igure 5. b aud r ate g enerator and p rescaler ..................................................................................................................... 13 t able 6: t ypical data rates with a 14.7456 mh z crystal or external clock ...................................................................... 13 2.12.1 transmit holding register (thr) - write only.......................................................................... ............. 14 2.12.2 transmitter operation in non-fifo mode ................................................................................ ................ 14 2.12.3 transmitter operation in fifo mode .................................................................................... ..................... 14 f igure 6. t ransmitter o peration in non -fifo m ode .............................................................................................................. 14 f igure 7. t ransmitter o peration in fifo and f low c ontrol m ode ..................................................................................... 14 2.13 receiver ............................................................................................................... ..................................... 15 2.13.1 receive holding register (rhr) - read-only ............................................................................ .............. 15 f igure 8. r eceiver o peration in non -fifo m ode .................................................................................................................... 15 2.14 auto rts hardware flow control ......................................................................................... ....... 16 2.15 auto rts hysteresis ................................................................................................... ......................... 16 2.16 auto cts flow control ................................................................................................. .................... 16 f igure 9. r eceiver o peration in fifo and a uto rts f low c ontrol m ode ......................................................................... 16 2.17 auto xon/xoff (software) flow control .................................................................................. . 17 f igure 10. a uto rts and cts f low c ontrol o peration ....................................................................................................... 17 2.18 special character detect .............................................................................................. ................. 18 2.19 auto rs485 half-duplex control ........................................................................................ .......... 18 2.20 infrared mode .......................................................................................................... .............................. 18 t able 7: a uto x on /x off (s oftware ) f low c ontrol ............................................................................................................... 18 2.21 sleep mode with auto wake-up .......................................................................................... ............. 19 f igure 11. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding .......................................................................... 19 2.22 internal loopback ..................................................................................................... ......................... 20 f igure 12. i nternal l oop b ack in c hannels a-d ..................................................................................................................... 21 3.0 uart internal registers ................................................................................................. ..........22 t able 8: uart channel a and b uart internal registers............................................................................ .......... 22 t able 9: internal registers description. s haded bits are enabled when efr b it -4=1......................................... 23 4.0 internal register descriptions .......................................................................................... ...25 4.1 receive holding register (rhr) - read- only ............................................................................. .. 25 4.2 transmit holding register (thr) - write-only ............................................................................ 25 4.3 interrupt enable register (ier) - read/write ............................................................................ .. 25
? ? ? ? xr16c864 rev. 2.0.1 2.97v to 5.5v quad uart with 128-byte fifo 2 4.3.1 ier versus receive fifo interrupt mode operation ....................................................................... ...... 25 4.3.2 ier versus receive/transmit fifo polled mode operation................................................................ 25 4.4 interrupt status register (isr) - read-only ............................................................................. .. 26 4.4.1 interrupt generation: .................................................................................................. .................................... 26 4.4.2 interrupt clearing: .................................................................................................... ....................................... 26 4.5 fifo control register (fcr) - write-only ................................................................................ ..... 27 t able 10: i nterrupt s ource and p riority l evel ..................................................................................................................... 27 4.6 line control register (lcr) - read/write ................................................................................ ..... 29 t able 11: t ransmit and r eceive fifo t rigger l evel s election ............................................................................................ 29 t able 12: p arity selection ............................................................................................................................... ......................... 30 4.7 modem control register (mcr) or general purpose outputs control - read/write 31 t able 13: int o utput m odes ............................................................................................................................... ...................... 31 4.8 line status register (lsr) - read only .................................................................................. ......... 32 4.9 modem status register (msr) - read only ................................................................................. ... 33 4.10 scratch pad register (spr) - read/write ................................................................................ .... 34 4.11 enhanced mode select register (emsr) ................................................................................... ... 34 t able 14: s cratchpad s wap s election ............................................................................................................................... ..... 34 t able 15: a uto rts h ysteresis .............................................................................................................................. ................. 35 4.12 fifo level register (flvl) - read-only ................................................................................. ........ 35 4.13 baud rate generator registers (dll and dlm) - read/write .............................................. 35 4.14 device identification register (dvid) - read only .................................................................... 3 5 4.15 device revision register (drev) - read only ............................................................................ .. 35 4.16 trigger level (trg) - write-only ....................................................................................... .............. 35 4.17 fifo data count register (fc) - read-only .............................................................................. ... 36 4.18 feature control register (fctr) - read/write ....................................................................... 36 4.19 enhanced feature register (efr) - read/write ........................................................................ 36 t able 16: t rigger t able s elect ............................................................................................................................... ................ 36 t able 17: s oftware f low c ontrol f unctions ........................................................................................................................ 37 4.20 software flow control registers (xoff1, xoff2, xon1, xon2) - read/write ................ 38 4.21 fifo status register (fstat) - read/write .............................................................................. ..... 38 t able 18: uart reset conditions for channels a-d ................................................................................... .............. 39 electrical characteristics................................................................................ 40 a bsolute m aximum r atings ..................................................................................................................... 40 t ypical package thermal resistance data (m argin of error : 15%) ................................................ 40 dc e lectrical c haracteristics .............................................................................................................. 40 ac e lectrical c haracteristics .............................................................................................................. 41 ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.97 to 5.5v ........................ 41 f igure 13. c lock t iming ............................................................................................................................... .............................. 42 f igure 14. m odem i nput /o utput t iming f or c hannels a-d .................................................................................................... 42 f igure 15. 16 m ode (i ntel ) d ata b us r ead t iming for c hannels a-d ................................................................................... 43 f igure 16. 16 m ode (i ntel ) d ata b us w rite t iming for c hannels a-d .................................................................................. 43 f igure 17. 68 m ode (m otorola ) d ata b us r ead t iming for c hannels a-d........................................................................... 44 f igure 18. 68 m ode (m otorola ) d ata b us w rite t iming for c hannels a-d ......................................................................... 44 f igure 19. r eceive r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a-d ............................................................ 45 f igure 20. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a-d .......................................................... 45 f igure 21. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ] for c hannels a-d........................................... 46 f igure 22. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ] for c hannels a-d............................................ 46 f igure 23. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] for c hannels a-d .............................. 47 p ackage d imensions ............................................................................................................................... .. 48 r evision h istory ............................................................................................................................... ....... 49 t able of c ontents ........................................................................................................... 1

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